The present application relates generally to analog-to-digital conversion and, more particularly, to calibrating stages in pipeline analog-to-digital converters (ADCs).
Pipeline ADCs are a preferred architecture for medium to high speed, high resolution ADCs. They have low power consumption and relatively low comparator accuracy compared to flash ADCs and high throughput due to the pipelining of lower accuracy stages compared to cyclic ADCs. A pipeline ADC is a switched capacitor circuit relying on capacitor matching and high op-amp open loop gain to achieve high accuracy. In applications where distortion must be very low, calibration of capacitor mismatches and finite op-amp open loop gain is needed. Ideally, the calibration circuitry does not substantially increase the complexity of the design or impact operation speed. However, in practical implementations, the additional circuitry needed for calibration is significant and may severely limit obtainable conversion speed.